Table 7. AC Characteristics (SYSCLK Freq. = 25 MHz − 5V ±10%) Cload = 50 pF, Vref = 2.5V (Continued)
Min
(ns)
Max
(ns)
Parameter
Comment
Reference Edge
SYSCLK+
t24
t25
12
0
–
–
BUSRDY* setup time
BUSRDY* hold time
SYSCLK+
SYSCLK+ HL
SYSCLK- LH
IOSEL output delay
t27
t28
t29
–
12
0
15
20
20
DMAAS setup time
formula of max: 1/2 t2
SYSCLK+
DMAAS hold time
formula of max: 1/2 t2
SYSCLK-
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
-
t30
t31
t32
t33
t36
t37
t38
t39
t40
t41
t46
t48
t49
t50
t52
t53
t54
t56
t57
t60
12
–
–
15
–
DMAREQ* setup time
DMAGNT* output delay
RA(31:0) RAPAR CPAR setup time
RA(31:0) RAPAR CPAR hold time
TCK period
10
3
–
100
10
4
–
–
TMS setup time
TCK+
–
TMS hold time
TCK+
10
10
–
–
TDI setup time
TCK+
–
TDI hold time
TCK+
20
22
22
20
20
–
TDO output delay
TCK-
–
INULL output delay
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK-
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
–
RESET* CPUHALT* output delay
SYSERR* SYSAV output delay
IUERR* output delay
–
–
12
0
EXTINT(4:0) setup time
EXTINT(4:0) hold time
EXTINTACK output delay
OE* LH output delay (no DMA mode)
BUFFEN* LH output delay
INST output delay
–
–
15
8.5
9
–
–
–
22
Data output delay to low-Z – guaranteed by design
formula: 10 ns + 1/4 t2
t61
t80
t81
20
12
0
–
SYSCLK+
SYSCLK+
BUSERR* setup time
BUSERR* hold time
formula: 24 ns + t2
64
SYSCLK+
16
TSC695F
4118J–AERO–08/04
ATMEL [ ATMEL ]
