TSC695F
Test and Diagnostic
Hardware Functions
A variety of TSC695F test and diagnostic hardware functions, including boundary scan,
internal scan, clock control and On-chip Debugger, are controlled through an IEEE
1149.1 (JTAG) standard Test Access Port (TAP).
Test Access Port
The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695F chip. These
pins are:
•
•
•
•
•
TCK (input): Test Clock
TMS (input): Test Mode Select
TDI (input): Test Data Input
TDO (output): Test Data Output
TRST (input): Test Reset
Instruction Register
Five standard instructions are supported by the TSC695F TAP.
Binary Value Name of Instruction Data Register Scan Chain Accessed
00. 0000
00. 0001
00. 0011
EXTEST
Boundary Scan
Register
Boundary scan chain
Boundary scan chain
Boundary scan chain
SAMPLE/PRELOAD
INTEST
Boundary Scan
Register
Boundary Scan
Register
11. 1111
10. 0000
BYPASS
IDCODE
Bypass Register
Bypass register
Device ID Register
ID register scan chain
Debugging
The design is highly testable with the support of an On-Chip Debugger (OCD), an inter-
nal and boundary scan through JTAG interface.
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4118J–AERO–08/04
ATMEL [ ATMEL ]
