AT90USB82/162
Figure 6-6. PLL Clocking System
PLLE
PLOCK
Lock
Detector
clk
8MHz
clk
USB (48MHz)
PLL clock
Prescaler
PLL
6x
System Clock
Clock Mux (fuse)
Clock Switch
Int RC
8MHz.
XTAL2
Ext.
XTAL
XTAL1
6.9.2
PLL Control and Status Register – PLLCSR
Bit
7
6
5
4
3
2
1
0
$29 ($29)
Read/Write
Initial Value
PLLP2
PLLP1
PLLP0
PLLE
R/W
0/1
PLOCK
PLLCSR
R
0
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT90USB82/162 and always read as zero.
• Bit 4..2 – PLLP2:0 PLL prescaler
These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the
PLL.
Table 6-10. PLL input prescaler configurations
PLLP2
PLLP1
PLLP0
Clock Division Factor
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL
reference clock. If PLL is selected as a system clock source the value for this bit is always 1.
37
7707D–AVR–07/08
ATMEL [ ATMEL ]
