Figure 25-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLPH
tXLXH
tPLXH
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 25-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-
ing operation.
Figure 25-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLOL
XTAL1
BS1
tBVDV
tOLDV
OE
tOHDZ
ADDR1 (Low Byte)
DATA (High Byte)
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 25-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-
ing operation.
Table 25-13. Parallel Programming Characteristics, VCC = 5V ± 10%
Symbol
VPP
Parameter
Min
Typ
Max
12.5
250
Units
V
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
11.5
IPP
μA
ns
tDVXH
tXLXH
tXHXL
tXLDX
67
200
150
67
ns
ns
Data and Control Hold after XTAL1 Low
ns
256
AT90USB82/162
7707D–AVR–07/08
ATMEL [ ATMEL ]
