AT90USB82/162
20.13.1.1
“Manual” mode
Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an
interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing
the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the cur-
rent bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will
switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in
accordance with the status of the new bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
read data from the bank, and cleared by hardware when the bank is empty.
Example with 1 OUT data bank
DATA
OUT
NAK
DATA
(to bank 0)
ACK
HW
OUT
ACK
HW
(to bank 0)
RXOUTI
SW
SW
read data from CPU
BANK 0
FIFOCON
SW
read data from CPU
BANK 0
Example with 2 OUT data banks
DATA
OUT
DATA
(to bank 1)
ACK
HW
OUT
ACK
(to bank 0)
HW
RXOUTI
SW
SW
read data from CPU
BANK 0
SW
FIFOCON
read data from CPU
BANK 1
20.13.2 Detailed description
The data are read by the CPU, following the next flow:
• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled
(RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending
on the software architecture,
• The CPU acknowledges the interrupt by clearing RXOUTI,
• The CPU can read the number of byte (N) in the current bank (N=BYCT),
• The CPU can read the data from the current bank (“N” read of UEDATX),
203
7707D–AVR–07/08
ATMEL [ ATMEL ]
