AT90USB82/162
Table 17-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz
U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1
UBRR UBRR UBRR UBRR UBRR UBRR
Baud
Rate
(bps)
Error
-0.1%
0.2%
0.2%
0.6%
0.2%
-0.8%
0.2%
2.1%
0.2%
-3.5%
8.5%
0.0%
0.0%
0.0%
Error
0.0%
-0.1%
0.2%
-0.1%
0.2%
0.6%
0.2%
-0.8%
0.2%
2.1%
-3.5%
0.0%
0.0%
0.0%
Error
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
-7.8%
–
Error
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
0.0%
2.4%
-7.8%
–
Error
0.0%
0.2%
0.2%
-0.2%
0.2%
0.9%
-1.4%
-1.4%
1.7%
-1.4%
8.5%
0.0%
–
Error
0.0%
0.0%
0.2%
-0.2%
0.2%
-0.2%
0.2%
0.9%
-1.4%
-1.4%
-1.4%
0.0%
0.0%
–
2400
4800
9600
14.4k
19.2k
28.8k
38.4k
57.6k
76.8k
115.2k
230.4k
250k
416
207
103
68
51
34
25
16
12
8
832
416
207
138
103
68
51
34
25
16
8
479
239
119
79
59
39
29
19
14
9
959
479
239
159
119
79
59
39
29
19
9
520
259
129
86
64
42
32
21
15
10
4
1041
520
259
173
129
86
64
42
32
21
3
4
10
3
7
4
8
4
9
0.5M
1M
1
3
–
4
–
4
0
1
–
–
–
–
–
–
Max. (1)
1 Mbps
UBRR = 0, Error = 0.0%
2 Mbps
1.152 Mbps
2.304 Mbps
1.25 Mbps
2.5 Mbps
1.
18. USART in SPI Mode
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be
set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow-
ing features:
• Full Duplex, Three-wire Synchronous Data Transfer
• Master Operation
• Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
• LSB First or MSB First Data Transfer (Configurable Data Order)
• Queued Operation (Double Buffered)
• High Resolution Baud Rate Generator
• High Speed Operation (fXCKmax = fCK/2)
• Flexible Interrupt Generation
18.1 Overview
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-
tion the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate gen-
erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX
173
7707D–AVR–07/08
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