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90USB82-16MU 参数 Datasheet PDF下载

90USB82-16MU图片预览
型号: 90USB82-16MU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8 / 16K字节 [8-bit Microcontroller with 8/16K Bytes of ISP Flash]
分类和应用: 微控制器和处理器外围集成电路异步传输模式ATM时钟
文件页数/大小: 306 页 / 2299 K
品牌: ATMEL [ ATMEL ]
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AT90USB82/162  
15.4 Counter Unit  
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.  
Figure 15-2 shows a block diagram of the counter and its surroundings.  
Figure 15-2. Counter Unit Block Diagram  
DATA BUS (8-bit)  
TOVn  
(Int.Req.)  
TEMP (8-bit)  
Clock Select  
Count  
Clear  
Edge  
Detector  
Tn  
TCNTnH (8-bit)  
TCNTnL (8-bit)  
clkTn  
Control Logic  
Direction  
TCNTn (16-bit Counter)  
( From Prescaler )  
TOP  
BOTTOM  
Signal description (internal signals):  
Count  
Increment or decrement TCNTn by 1.  
Direction  
Clear  
Select between increment and decrement.  
Clear TCNTn (set all bits to zero).  
clkT  
Timer/Counter clock.  
n
TOP  
Signalize that TCNTn has reached maximum value.  
BOTTOM  
Signalize that TCNTn has reached minimum value (zero).  
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-  
taining the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight  
bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an  
access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).  
The temporary register is updated with the TCNTnH value when the TCNTnL is read, and  
TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the  
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.  
It is important to notice that there are special cases of writing to the TCNTn Register when the  
counter is counting that will give unpredictable results. The special cases are described in the  
sections where they are of importance.  
Depending on the mode of operation used, the counter is cleared, incremented, or decremented  
at each timer clock (clk ). The clk n can be generated from an external or internal clock source,  
n
T
T
selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the  
timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of  
whether clkT is present or not. A CPU write overrides (has priority over) all counter clear or  
n
count operations.  
The counting sequence is determined by the setting of the Waveform Generation mode bits  
(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).  
There are close connections between how the counter behaves (counts) and how waveforms  
are generated on the Output Compare outputs OCnx. For more details about advanced counting  
sequences and waveform generation, see “Modes of Operation” on page 119.  
113  
7707D–AVR–07/08  
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