corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
11.0.7
Pin Change Mask Register 0 – PCMSK0
Bit
7
6
5
4
3
2
1
0
PCINT7
PCINT6
PCINT5
R/W
0
PCINT4
R/W
0
PCINT3
R/W
0
PCINT2
R/W
0
PCINT1
R/W
0
PCINT0
R/W
0
PCMSK0
Read/Write
Initial Value
R/W
0
R/W
0
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin
is disabled.
98
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
