Table 11-1.
Interrupt Sense Control(1)
ISCn0 Description
ISCn1
0
0
1
1
0
1
0
1
The low level of INTn generates an interrupt request.
Any edge of INTn generates asynchronously an interrupt request.
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
Note:
1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Table 11-2. Asynchronous External Interrupt Characteristics
Symbol Parameter Condition Min
Minimum pulse width for
Typ
Max
Units
tINT
50
ns
asynchronous external interrupt
11.0.2
External Interrupt Control Register B – EICRB
Bit
7
6
5
4
3
2
1
0
ISC71
R/W
0
ISC70
R/W
0
ISC61
R/W
0
ISC60
R/W
0
ISC51
R/W
0
ISC50
R/W
0
ISC41
R/W
0
ISC40
R/W
0
EICRB
Read/Write
Initial Value
• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in Table 11-3. The value on the INT7:4 pins are sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled. If low level interrupt is selected, the low level must be held until the comple-
tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered
interrupt will generate an interrupt request as long as the pin is held low.
Table 11-3.
ISCn1 ISCn0 Description
Interrupt Sense Control(1)
0
0
0
1
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request
The falling edge between two samples of INTn generates an interrupt
request.
1
0
1
The rising edge between two samples of INTn generates an interrupt
request.
1
Note:
1. n = 7, 6, 5 or 4.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
11.0.3
96
External Interrupt Mask Register – EIMSK
Bit
7
6
5
4
3
2
1
0
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
