AT90USB64/128
Figure 29-15. State Machine Sequence for Changing/Reading the Data Word
1
Test-Logic-Reset
0
1
1
1
0
Run-Test/Idle
Select-DR Scan
Select-IR Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
Shift-DR
0
Shift-IR
0
1
Exit1-DR
0
1
1
1
Exit1-IR
0
Pause-IR
1
Pause-DR
1
0
0
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
1
0
0
29.9.11 Flash Data Byte Register
The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer
before executing Page Write, or to read out/verify the content of the Flash. A state machine sets
up the control signals to the Flash and senses the strobe signals from the Flash, thus only the
data words need to be shifted in/out.
The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary reg-
ister. During page load, the Update-DR state copies the content of the scan chain over to the
temporary register and initiates a write sequence that within 11 TCK cycles loads the content of
the temporary register into the Flash page buffer. The AVR automatically alternates between
writing the low and the high byte for each new Update-DR state, starting with the low byte for the
first Update-DR encountered after entering the PROG_PAGELOAD command. The Program
Counter is pre-incremented before writing the low byte, except for the first written byte. This
ensures that the first data is written to the address set up by PROG_COMMANDS, and loading
the last location in the page buffer does not make the Program Counter increment into the next
page.
During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte
Register during the Capture-DR state. The AVR automatically alternates between reading the
low and the high byte for each new Capture-DR state, starting with the low byte for the first Cap-
395
7593A–AVR–02/06
ATMEL [ ATMEL ]
