AT90S1200
Reading the Signature Bytes
The algorithm for reading the signature bytes is as follows (refer to “Programming the
Flash” on page 39 for details on command and address loading):
1. A: Load Command “0000 1000”.
2. C: Load Address Low Byte ($00 - $02).
Set OE to “0”, and BS to “0”. The selected signature byte can now be read at DATA.
Set OE to “1”.
Parallel Programming
Characteristics
Figure 33. Parallel Programming Timing
tXLWL
tXHXL
XTAL1
tDVXH
tXLDX tBVWL
Data & Contol
(DATA, XA0/1, BS)
tWLWH
WR
tRHBX
tWHRL
RDY/BSY
tWLRH
tOHDZ
OE
tXLOL
tOLDV
DATA
Table 17. Parallel Programming Characteristics, TA = 25°C 10%, VCC = 5V 10%
Symbol
VPP
Parameter
Min
Typ
Max
12.5
Units
V
Programming Enable Voltage
Programming Enable Current
Data and Control Setup before XTAL1 High
XTAL1 Pulse Width High
11.5
IPP
250.0
µA
ns
tDVXH
tXHXL
tXLDX
tXLWL
tBVWL
tRHBX
tWLWH
tWHRL
tWLRH
tXLOL
67.0
67.0
67.0
67.0
67.0
67.0
67.0
ns
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
ns
ns
BS Valid to WR Low
ns
BS Hold after RDY/BSY High
WR Pulse Width Low(1)
ns
ns
WR High to RDY/BSY Low(2)
WR Low to RDY/BSY High(2)
XTAL1 Low to OE Low
20.0
0.7
ns
0.5
0.9
ms
ns
67.0
tOLDV
tOHDZ
tWLWH_CE
OE Low to DATA Valid
20.0
ns
OE High to DATA Tri-stated
WR Pulse Width Low for Chip Erase
20.0
15.0
1.8
ns
5.0
1.0
10.0
1.5
ms
ms
tWLWH_PFB WR Pulse Width Low for Programming the Fuse
Bits
Notes: 1. Use tWLWH_CE for chip erase and tWLWH_PFB for programming the Fuse bits.
2. If tWLWH is held longer than tWLRH, no RDY/BSY pulse will be seen.
43
0838H–AVR–03/02
ATMEL [ ATMEL ]
