Table 29. Read MOVC A, @DPTR
FCON Register
Hardware
Byte
Code Execution FMOD1 FMOD0
FPS
ENBOOT
DPTR
FM1
FM0
OK
XROW
0
0000h to 3FFFh
0000h to 3FFFh
F800h to FFFFh
0
0
X
OK
1
Do not use this configuration
OK
0000 to 007Fh
See (1)
0
1
1
0
X
X
X
From FM0
X
0
X
OK
000h to 3FFFh
0000h to 3FFFh
F800h to FFFFh
0000h to 3FFF
F800h to FFFFh
X
OK
1
1
X
0
OK
1
1
Do not use this configuration
OK
OK
0
0
0
1
0
1
0
1
0
1
0
NA
OK
X
1
X
X
X
X
NA
From FM1
OK
0000h to 007h
See (2)
(ENBOOT =1
0
1
1
1
0
1
NA
OK
X
NA
OK
000h to 3FFFh
NA
1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from
0000h to 007Fh
2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from
0000h to 007Fh
44
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
