10.3 Registers
Table 35. IEN0 Register
IEN0 (S:A8h) – Interrupt Enable Register 0
7
6
5
–
4
3
2
1
0
EA
EAUD
ES
ET1
EX1
ET0
EX0
Bit
Bit Number Mnemonic Description
Enable All Interrupt Bit
Set to enable all interrupts.
Clear to disable all interrupts.
7
EA
If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing
its interrupt enable bit.
Audio Interface Interrupt Enable Bit
Set to enable audio interface interrupt.
Clear to disable audio interface interrupt.
6
5
4
EAUD
–
Reserved
The values read from this bit is always 0. Do not set this bit.
Serial Port Interrupt Enable Bit
Set to enable serial port interrupt.
Clear to disable serial port interrupt.
ES
Timer 1 Overflow Interrupt Enable Bit
Set to enable Timer 1 overflow interrupt.
Clear to disable Timer 1 overflow interrupt.
3
2
1
0
ET1
EX1
ET0
EX0
External Interrupt 1 Enable bit
Set to enable external interrupt 1.
Clear to disable external interrupt 1.
Timer 0 Overflow Interrupt Enable Bit
Set to enable timer 0 overflow interrupt.
Clear to disable timer 0 overflow interrupt.
External Interrupt 0 Enable Bit
Set to enable external interrupt 0.
Clear to disable external interrupt 0.
Reset Value = 0000 0000b
Table 36. IEN1 Register
IEN1 (S:B1h) – Interrupt Enable Register 1
7
-
6
5
–
4
3
2
1
0
EUSB
EKB
EADC
ESPI
EI2C
EMMC
38
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
