AT89C5132
Table 33. Priority Levels
IPHxx
IPLxx
Priority Level
0
0
1
1
0
1
0
1
0 Lowest
1
2
3 Highest
A low-priority interrupt is always interrupted by a higher priority interrupt but not by another inter-
rupt of lower or equal priority. Higher priority interrupts are serviced before lower priority
interrupts. The response to simultaneous occurrence of equal priority interrupts is determined by
an internal hardware polling sequence detailed in Table 34. Thus within each priority level there
is a second priority structure determined by the polling sequence. The interrupt control system is
shown in Figure 10-1.
Table 34. Priority Within Same Level
Interrupt Request Flag
Cleared by Hardware (H)
Interrupt Name
INT0
Priority Number
Interrupt Address Vectors
C:0003h
or by Software (S)
0 (Highest Priority)
H if edge, S if level
Timer 0
1
C:000Bh
H
INT1
2
C:0013h
H if edge, S if level
Timer 1
3
C:001Bh
H
S
Serial Port
Reserved
4
C:0023h
5
Audio Interface
MMC Interface
Two-wire Controller
SPI Controller
A-to-D Converter
Keyboard
6
C:0033h
C:003Bh
C:0043h
C:004Bh
C:0053h
C:005Bh
C:0063h
C:006Bh
C:0073h
S
S
S
S
S
S
-
7
8
9
10
11
Reserved
12
13
USB
S
-
Reserved
14 (Lowest Priority)
35
4173E–USB–09/07
ATMEL [ ATMEL ]
