AT89C5132
8.4
Registers
Table 13. PSW Register
PSW (S:8Eh) – Program Status Word Register
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Bit Number Mnemonic Description
Carry Flag
Carry out from bit 1 of ALU operands.
7
CY
Auxiliary Carry Flag
6
5
AC
F0
Carry out from bit 1 of addition operands.
User Definable Flag 0.
Register Bank Select Bits
Refer to Table 10 for Bits description.
4 - 3
RS1:0
Overflow Flag
Overflow set by arithmetic operations.
2
1
OV
F1
User Definable Flag 1
Parity Bit
0
P
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
Reset Value = 0000 0000b
Table 14. AUXR Register
AUXR (S:8Eh) – Auxiliary Control Register
7
-
6
5
4
3
2
1
0
EXT16
M0
DPHDIS
XRS1
XRS0
EXTRAM
AO
Bit
Bit Number Mnemonic Description
Reserved
The values read from this bit is indeterminate. Do not set this bit.
7
6
-
External 16-bit Access Enable Bit
Set to enable 16-bit access mode during MOVX instructions.
EXT16
Clear to disable 16-bit access mode and enable standard 8-bit access mode during
MOVX instructions.
External Memory Access Stretch Bit
Set to stretch RD or WR signals duration to 15 CPU clock periods.
Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
5
M0
DPH Disable Bit
Set to disable DPH output on P2 when executing MOVX @DPTR instruction.
Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.
4
DPHDIS
XRS1:0
Expanded RAM Size Bits
Refer to Table 11 for ERAM size description.
3 - 2
27
4173E–USB–09/07
ATMEL [ ATMEL ]
