Table 19. Port SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
P0
P1
P2
P3
P4
P5
80h 8-bit Port 0
90h 8-bit Port 1
A0h 8-bit Port 2
B0h 8-bit Port 3
C0h 8-bit Port 4
D8h 4-bit Port 5
-
-
-
-
Table 20. Flash Memory SFR
Mnemonic Add Name
7
6
5
4
3
2
1
0
FCON
D1h Flash Control
FPL3
FPL2
FPL1
FPL0
FPS
FMOD1
FMOD0
FBUSY
Table 21. Timer SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
TCON
TMOD
TL0
88h Timer/Counter 0 and 1 Control
TF1
TR1
TF0
M11
TR0
M01
IE1
IT1
IE0
M10
IT0
M00
89h Timer/Counter 0 and 1 Modes
8Ah Timer/Counter 0 Low Byte
8Ch Timer/Counter 0 High Byte
8Bh Timer/Counter 1 Low Byte
8Dh Timer/Counter 1 High Byte
A6h WatchDog Timer Reset
GATE1
C/T1#
GATE0
C/T0#
TH0
TL1
TH1
WDTRST
WDTPRG
A7h WatchDog Timer Program
-
-
-
-
-
WTO2
WTO1
WTO0
Table 22. Audio Interface SFRs
Mnemonic Add Name
7
6
5
4
3
JUST0
-
2
POL
DUP1
-
1
0
AUDCON0
AUDCON1
AUDSTA
AUDDAT
AUDCLK
9Ah Audio Control 0
9Bh Audio Control 1
9Ch Audio Status
JUST4
SRC
SREQ
AUD7
-
JUST3
DRQEN
UDRN
AUD6
-
JUST2
MSREQ
AUBUSY
AUD5
-
JUST1
MUDRN
-
DSIZ
DUP0
-
HLR
AUDEN
-
-
9Dh Audio Data
AUD4
AUCD4
AUD3
AUCD3
AUD2
AUCD2
AUD1
AUCD1
AUD0
AUCD0
ECh Audio Clock Divider
30
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
