AT89C5132
The next 16 Bytes above the register banks form a block of bit-addressable memory space. The
C51 instruction set includes a wide selection of single-bit instructions, and the 128 Bits in this
area can be directly addressed by these instructions. The bit addresses in this area are 00h to
7Fh.
Figure 8-2. Lower 128 Bytes Internal RAM Organization
7Fh
30h
2Fh
Bit-Addressable Space
(Bit Addresses 0 - 7Fh)
20h
1Fh
18h
17h
0Fh
07h
4 Banks of
8 Registers
R0 - R7
10h
08h
00h
8.1.2
8.1.3
Upper 128 Bytes RAM
The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
addressing mode.
Expanded RAM
The on-chip 2K Bytes of expanded RAM (ERAM) are accessible from address 0000h to 07FFh
using indirect addressing mode through MOVX instructions. In this address range, EXTRAM bit
in AUXR register (see Table 14) is used to select the ERAM (default) or the XRAM. As shown in
Figure 8-1 when EXTRAM = 0, the ERAM is selected and when EXTRAM = 1, the XRAM is
selected, See “External Space” on page 23.
The ERAM memory can be resized using XRS1:0 Bits in AUXR register to dynamically increase
external access to the XRAM space. Table 11 details the selected ERAM size and address
range.
Table 11. ERAM Size Selection
XRS1
XRS0
ERAM Size
256 Bytes
512 Bytes
1K Byte
Address
0
0
1
1
0
1
0
1
0 to 00FFh
0 to 01FFh
0 to 03FFh
0 to 07FFh
2K Bytes
Note:
Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile memory
cells. This means that the RAM content is indeterminate after power-up and must then be initial-
ized properly.
8.2
External Space
8.2.1
Memory Interface
The external memory interface comprises the external bus (port 0 and port 2) as well as the bus
control signals (RD, WR, and ALE).
23
4173E–USB–09/07
ATMEL [ ATMEL ]
