Registers
Table 94. DFCON Register
DFCON (1.89h) – DFC Control Register
7
6
5
4
3
2
1
0
-
DFRES
-
DFCRCEN DFPRIO1
DFPRIO0
DFABTM
DFEN
Bit
Bit
Number
Mnemonic Description
Reserved
5
6
5
-
The value read from this bit is always 0. Do not set this bit.
Data Flow Controller Reset Bit
DFRES
-
Set then clear this bit to reset the Data Flow Controller by software.
Reserved
The value read from this bit is always 0. Do not set this bit.
CRC Enable Bit
4
3-2
1
DFCRCEN
DFPRIO1:0
DFABTM
Set to enable CRC calculation on channel 0.
Clear to disable CRC calculation.
Data Flow Channel Priority Assignment Bits
Refer to Table 93 for channel priority assignment description.
Data Flow Abort Mode Bit
Set to trigger a delayed abort.
Clear to trigger an immediate abort.
Data Flow Controller Enable Bit
0
DFEN
Set to enable the Data Flow Controller.
Clear to disable the Data Flow Controller.
Reset Value = 0000 0000b
Table 95. DFCSTA Register
DFCSTA (1.88h Bit Addressable) – DFC Channel Status Register
7
6
5
4
3
2
1
0
DRDY1
SRDY1
EOFI1
DFBSY1
DRDY0
SRDY0
EOFI0
DFBSY0
Bit
Bit
Number
Mnemonic Description
Channel 1 Destination Ready Flag
7
6
5
4
DRDY1
SRDY1
EOFI1
Set by hardware when the destination peripheral of channel 1 is ready.
Cleared by hardware when the destination peripheral of channel 1 is not ready.
Channel 1 Source Ready Flag
Set by hardware when the source peripheral of channel 1 is ready.
Cleared by hardware when the source peripheral of channel 1 is not ready.
Channel 1 End Of Data Flow Interrupt Flag
Set by hardware at the end of a channel 1 data flow transfer.
Cleared by software by setting EOFIA1 in DFCCON. Can not be set by software.
Channel 1 Busy Flag
DFBSY1
Set by hardware when a transfer is on-going on channel 1.
Cleared by hardware when no transfer is on-going on channel 1.
82
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
