AT85C51SND3Bx
Figure 46. Immediate Data Flow Abort Diagram
DP
Data bus
DFABTx
DFBSYx
N+2
N+1
N
Remaining DP
Figure 47. Delayed Data Flow Abort Diagram
DP
DP
Data bus
DFABTx
DFBSYx
N+2
N+1
N
Remaining DP
Data Flow Configuration Prior to any operation, the DFC must be configured in term of clock source and channel
priority, then DFC can be enabled.
Each time a data flow must be established, a data flow descriptor must be written to the
DFC.
Interrupts
As shown in Figure 48, the DFC interrupt request is generated by 2 different sources:
the EOFI0 flag or EOFI1 flag in DFCSTA. Both sources can be enabled separately by
using the EOFE0 and EOFE1 bits in DFCCON. A global enable of the DFC interrupt is
provided by setting the EDFC bit in IENx register.
The interrupt is requested each time one of the 2 sources is asserted.
EOFI0 or EOFI1 flags are set:
•
•
•
at the end of a data flow on respective channel.
after an immediate abort command at the end of the byte transfer.
after a delayed abort at the end of the data packet transfer.
Note:
An abort command never sets flags while in the process of writing DFD.
EOFI0 and EOFI1 flags must be cleared by software by setting EOFIA0 and EOFIA1
bits in DFCCON, in order to acknowledge the interrupt. Setting these flags by software
has no effect.
Figure 48. DFC Interrupt System
EOFI0
DFCSTA.1
DFC
Interrupt
Request
EOFE0
DFCCON.2
EOFI1
DFCSTA.5
EDFC
IENx.y
EOFE1
DFCCON.6
81
7632A–MP3–03/06
ATMEL [ ATMEL ]
