AT85C51SND3Bx
Table 33. CKSEL Register
CKSEL (0.BAh) – Clock Selection Register
7
6
5
4
3
2
1
0
DNFCKS2 DNFCKS1 DFCCKS0
PLLCKS1
PLLCKS0
SIOCKS
SYSCKS1 SYSCKS0
Bit
Bit
Number
Mnemonic Description
DFC/NFC Clock Select Bits
7-5
4-3
2
DNFCKS2:0
PLLCKS1:0
SIOCKS
Refer to Table 27 for information on selected clock value.
PLL Reverse Clock Select Bits
Refer to Table 24 for information on selected clock value.
SIO Clock Select Bit
Refer to Table 30 for information on divided clock value.
System Clock Select Bits
1-0
SYSCKS1:0
Refer to Table 26 for information on divided clock value.
Reset Value = 0000 0000b
Table 34. PLLCLK Register
PLLCLK (0.BCh) – PLL Clock Control Register
7
6
5
4
3
2
1
0
PLLR3
PLLR2
PLLR1
PLLR0
PLLN3
PLLN2
PLLN1
PLLN0
Bit
Bit
Number
Mnemonic Description
PLL R Divider Bits
7-4
3-0
PLLR3:0
PLLN3:0
4-bit R divider, R from 1 (PLLR3:0 = 0000) to 16 (PLLR3:0 = 1111).
PLL N Divider Bits
4-bit N divider, N from 1 (PLLN3:0 = 0000) to 16 (PLLN3:0 = 1111).
Reset Value = 0000 0000b
Table 35. MMCCLK Register
MMCCLK (0.BDh) – MMC Clock Control Register
7
6
5
4
3
2
1
0
MMCCKS2 MMCCKS1 MMCCKS0 MMCDIV4 MMCDIV3 MMCDIV2 MMCDIV1 MMCDIV0
Bit
Bit
Number
Mnemonic Description
MMC Clock Select Bits
7-5
4-0
MMCCKS2:0
MMCDIV4:0
Refer to Table 28 for information on selected clock value.
MMC Clock Divider Bits
Refer to Table 29 for information on divided clock value.
Reset Value = 0000 0000b
35
7632A–MP3–03/06
ATMEL [ ATMEL ]
