AT85C51SND3Bx
Registers
Table 31. CKCON Register
CKCON (0.8Fh) – Clock Control Register
7
6
5
4
3
2
1
0
-
WDX2
OSCAMP
OSCF1
OSCF0
T1X2
T0X2
X2
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The value read from this bit is always 0. Do not set this bit.
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2
independent).
WDX2
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
Oscillator Amplifier Control Bit
Set to optimize power consumption by disabling the oscillator amplifier when an
external clock is used.
Clear to enable the oscillator amplifier in case of crystal usage (default).
5
4-3
2
OSCAMP
OSCF1:0
T1X2
Oscillator Frequency Range Bits
Set this bits according to Table 23 to optimize power consumption.
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 1 clock input (X2
independent).
Clear to select the peripheral clock as timer 1 clock input (X2 dependent).
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 0 clock input (X2
independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
1
0
T0X2
X2
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER
FOSC/2).
=
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
Reset Value = 0000 0000b
33
7632A–MP3–03/06
ATMEL [ ATMEL ]
