AT85C51SND3Bx
Figure 21. DFC/NFC Clock Generator Block Diagram and Symbol
OSC
000
001
010
011
100
101
110
111
CKEN.0
60 MHz
48 MHz
40 MHz
30 MHz
24 MHz
20 MHz
16 MHz
DNFCKEN
FS
DFC Clock
NFC Clock
CLOCK
GEN
DNFC
CLOCK
DNFCKS2:0
CKSEL.7:5
DFC/NFC Clock Symbol
Table 27. DFC/NFC Clock Selection
DNFCKS2:0
000
Clock Selection (FS)
FOSC (default)
60 MHz
48 MHz
40 MHz
30 MHz
24 MHz
20 MHz
16 MHz
001
010
011
100
101
110
111
MMC Clock Generator
The MMC clock generator block diagram is shown in Figure 22 and is based on a fre-
quency selector followed by a frequency divider.
Frequency selection is done using MMCCKS2:0 bits in MMCCLK (see Table 35)
according to Table 28(1).
Frequency division is done using MMCDIV4:0 bits in MMCCLK according to Table 29.
Frequency configuration (selection and division) must be done prior to enable the MMC
clock generation by setting MMCKEN bit in CKEN.
Note:
1. To allow low frequency as low as 400 KHz (frequency needed in MMC identification
phase), FOSC selection can be divided by 2.
Figure 22. MMC Clock Generator Block Diagram and Symbol
OSC
000
CKEN.3
60 MHz
001
MMCKEN
48 MHz
010
30 MHz
24 MHz
20 MHz
16 MHz
FS
011
100
101
110
111
Clock
Divider
MMC Clock
CLOCK
GEN
OSC
÷ 2
MMCDIV4:0
MMCCLK.4:0
MMC
CLOCK
MMCCKS2:0
MMCCLK.7:5
MMC Clock Symbol
31
7632A–MP3–03/06
ATMEL [ ATMEL ]
