AT85C51SND3Bx
Table 180. ACOLG Register (AT85C51SND3B2 and AT85C51SND3B3 only)
ACOLG (2.ECh) – Audio Codec Left Output Gain Register
7
6
5
4
3
2
1
0
-
-
-
AOLG4
AOLG3
AOLG2
AOLG1
AOLG0
Bit
Bit
Number
Mnemonic Description
Reserved
7-5
4-0
-
The value read from these bits is always 0. Do not set these bits.
Audio Output Left Gain
AOLG4:0
Refer to Table 157 for gain value.
Reset Value = 0000 0000b
Table 181. ACIPG Register
ACIPG (2.EDh) – Audio Codec Input Preamplifier Gain Register
7
6
5
4
3
2
1
0
-
-
-
-
AILPG -
AIPG2
AIPG1
AIPG0
Bit
Bit
Number
Mnemonic Description
Reserved
7-4
3
-
The value read from these bits is always 0. Do not set these bits.
AT85C51SND3B2 and AT85C51SND3B3: Audio Input Line Preamplifier Gain
Refer to Table 161 for gain value.
AILPG
AT85C51SND3B1: Reserved
The value read from this bit is always 0. Do not set this bit.
Audio Input Preamplifier Gain
2-0
AIPG4:0
Refer to Table 160 for gain value.
Reset Value = 0000 0000b
Table 182. ADICON0 Register
ADICON0 (2.EEh) – Audio DAC Interface Control Register 0
7
6
5
4
3
2
1
0
-
-
-
CSPOL
DSIZE
OVERS1
OVERS0
ADIEN
Bit
Bit
Number
Mnemonic Description
Reserved
7-5
4
-
The value read from these bits is always 0. Do not set these bits.
Channel Select DSEL Signal Output Polarity Bit
CSPOL
DSIZE
Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I2S mode).
Audio Data Size Bit
3
Set to select 32-bit data output format.
Clear to select 16-bit data output format.
165
7632A–MP3–03/06
ATMEL [ ATMEL ]
