AT85C51SND3Bx
Bit
Bit
Number
Mnemonic Description
Reserved
2-1
0
-
The value read from these bits is always 0. Do not set these bits.
Audio Controller Clock Enable Bit
ACCKEN
Set to enable the Audio Controller Clock.
Clear to disable the Audio Controller Clock.
Reset Value = 0000 0000b
Table 166. APCON0 Register
APCON0 (1.F2h) – Audio Processor Control Register 0
7
6
5
4
3
2
1
0
0
APCMD6
APCMD5
APCMD4
APCMD3
APCMD2
APCMD1
APCMD0
Bit
Bit
Number
Mnemonic Description
Always 0
7
0
The value read from this bit is always 0. Can not be set by software.
Audio Processor Operating Command Bits
6-0
APCMD6:0
Codec firmware dependant.
Reset Value = 0000 0000b
Table 167. APCON1 Register
APCON1 (1.F3h) – Audio Processor Control Register 1
7
6
5
4
3
2
1
0
-
-
ABACC
ABWPR
ABRPR
ABSPLIT
APLOAD
DAPEN
Bit
Bit
Number
Mnemonic Description
Reserved
7-5
5
-
The value read from these bits is always 0. Do not set these bits.
Audio Buffer Access Bit
ABACC
ABWPR
Set to enable buffer access by C51 core.
Clear to enable buffer access by DFC.
Audio Buffer Write Pointer Reset Bit
Set to reset the audio buffer write pointer.
Cleared by hardware when write pointer is reset.
Can not be cleared by software.
4
Audio Buffer Read Pointer Reset Bit
Set to reset the audio buffer read pointer.
Cleared by hardware when read pointer is reset.
Can not be cleared by software.
3
2
ABRPR
Audio Buffer Split Bit
ABSPLIT
Set to configure the audio buffer as a double buffer.
Clear to configure the audio buffer as a single buffer.
159
7632A–MP3–03/06
ATMEL [ ATMEL ]
