AT85C51SND3Bx
The Figure 27 shows the memory segments configuration after bootstrap execution
along with an example of user memory segments configuration done during firmware
start-up. In this figure italicized address are the logical address within segments.
Figure 27. Memory Segment Configuration
FFh
FFh
FFFFh
FFFFh
256-byte DATA
256-byte DATA
00h
00h
FF00h
FEFFh
FF00h
FEFFh
MEMDBAX = 7Fh
MEMDBAX = 7Fh
EFFh
1EFFh
3840-byte XDATA MEMXSX = 0Eh
7936-byte XDATA MEMXSX = 1Eh
000h
F000h
EFFFh
MEMXBAX = 78h
EFFFh
000h
E000h
DFFFh
MEMXBAX = 70h
DFFFh
60-Kbyte CODE MEMCSX = EFh
56-Kbyte CODE MEMCSX = DFh
0000h
0000h
0000h
MEMCBAX = 00h
0000h
MEMCBAX = 00h
Default Configuration
User Configuration Example
Registers
Table 64. PSW Register
PSW (S:8Eh) – Program Status Word Register
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Bit
Number
Mnemonic Description
Carry Flag
7
CY
Carry out from bit 1 of ALU operands.
Auxiliary Carry Flag
6
5
AC
F0
Carry out from bit 1 of addition operands.
User Definable Flag 0
Register Bank Select Bits
4-3
RS1:0
Refer to Table 63 for bits description.
Overflow Flag
2
1
OV
F1
Overflow set by arithmetic operations.
User Definable Flag 1
Parity Bit
0
P
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
Reset Value = 0000 0000b
51
7632A–MP3–03/06
ATMEL [ ATMEL ]
