AT85C51SND3Bx
SFR Registers
The Special Function Registers (SFRs) of the AT85C51SND3Bx fall into the categories
detailed in Table 39 to Table 58. Address is identified as “P.XXh” where P can take the
values detailed in Table 38 and XXh is the hexadecimal address from 80h to FFh
Table 38. Page Address Notation
P
Y
Comment
Register mapped in all pages
Register mapped in the corresponding page
3-0
The SFRs mapping within pages is provided together with SFR reset value in Table 58
to Table 58. In these tables, the bit-addressable registers are identified by Note 1.
Table 39. C51 Core SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
ACC
B
Y.E0h Accumulator
Y.F0h B Register
PSW
SP
Y. D0h Program Status Word
Y.81h Stack Pointer
CY
AC
F0
RS1
RS0
OV
F1
P
DPL
DPH
PPCON
Y.82h Data Pointer Low Byte
Y.83h Data Pointer High Byte
Y. C0h Peripheral Pagination
-
-
-
-
PPS3:0
Table 40. Power and System Management
Mnemonic Add Name
7
6
5
4
3
DCEN*
-
2
1
0
PCON
PSTA
0.87h Power Control
VBCEN
UVDET
-
VBPEN
HVDET
-
DCPBST
GF0
PMLCK
PD
IDL
0.86h Power Status
-
-
-
-
-
WDTRST EXTRST PFDRST
AUXR1
VBAT
0.A2h Auxiliary Register 1
0.85h Battery Voltage Monitoring
GF3
0
-
DPS
VBEN
VBERR
VB4:0
SVERS
Note:
3.97h Silicon Version
SV7:0
Available in AT85C51SND3B3 only.
Table 41. Clock Management Unit SFRs
Mnemonic Add Name
7
6
5
-
4
3
2
T1X2
-
1
0
CKCON
CKEN
0.8Fh Clock Control
0.B9h Clock Enable
0.BAh Clock Selection
0.BCh PLL Clock
-
WDX2
OSCF1:0
T0X2
X2
CKGENE
PLLEN
-
PLOCK
MMCKEN
SIOCKEN DFCKEN
SYSCKS1:0
CKSEL
PLLCLK
DNFCKS2:0
PLLCKS1:0
SIOCKS
PLLR3:0
MMCCKS2:0
PLLN3:0
MMCDIV4:0
MMCCLK 0.BDh MMC Clock
37
7632A–MP3–03/06
ATMEL [ ATMEL ]
