CLK. Falling edge latches AUDCDIN input and rising edge shifts AUDCDOUT output
bits.
Note that the DLCK must run during any DAC SPI interface access (read or write).
Figure 60. DAC SPI Interface Timings
AUDCCS
Tc
Tssen
Thsen
Twl
AUDCCLK
Twh
Tssdi
Thsdi
AUDCDIN
Thsdo
Tdsdo
AUDCDOUT
Table 91. Dac SPI Interface Timings
Timing parameter
Description
Min
150 ns
Max
Tc
AUDCCLK min period
-
Twl
AUDCCLK min pulse width low
AUDCCLK min pulse width high
50 ns
50 ns
50 ns
50 ns
20 ns
20 ns
-
-
Twh
-
Tssen
Thsen
Tssdi
Thsdi
Tdsdo
Thsdo
Setup time AUDCCS falling to AUDCCLK rising
Hold time AUDCCLK falling to AUDCCS rising
Setup time AUDCDIN valid to AUDCCLK falling
Hold time AUDCCLK falling to AUDCDIN not valid
Delay time AUDCCLK rising to AUDCDOUT valid
Hold time AUDCCLK rising to AUDCDOUT not valid
-
-
-
-
20 ns
-
0 ns
84
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
