AT8xC51SND2C
Watchdog Timer
The AT8xC51SND2C implement a hardware Watchdog Timer (WDT) that automatically
resets the chip if it is allowed to time out. The WDT provides a means of recovering from
routines that do not complete successfully due to software or hardware malfunctions.
Description
The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As
shown in Figure 36, the 14-bit prescaler is fed by the WDT clock detailed in
Section “Watchdog Clock Controller”, page 59.
The Watchdog Timer Reset register (WDTRST, see Table 69) provides control access
to the WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 39) pro-
vides time-out period programming.
Three operations control the WDT:
•
•
•
Chip reset clears and disables the WDT.
Programming the time-out value to the WDTPRG register.
Writing a specific 2-Byte sequence to the WDTRST register clears and enables the
WDT.
Figure 36. WDT Block Diagram
14-bit Prescaler
7-bit Counter
WDT
CLOCK
÷ 6
OV
To internal reset
RST
RST
SET
WTO2:0
WDTPRG.2:0
1Eh-E1h Decoder
EN
RST
System Reset
MATCH
OSC
CLOCK
Pulse Generator
RST
WDTRST
Watchdog Clock
Controller
As shown in Figure 37 the WDT clock (FWDT) is derived from either the peripheral clock
(FPER) or the oscillator clock (FOSC) depending on the WTX2 bit in CKCON register.
These clocks are issued from the Clock Controller block as detailed in Section "Clock
Controller", page 12. When WTX2 bit is set, the WDT clock frequency is fixed and equal
to the oscillator clock frequency divided by 2. When cleared, the WDT clock frequency is
equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator
clock frequency in X2 mode.
Figure 37. WDT Clock Controller and Symbol
PER
CLOCK
0
WDT
CLOCK
WDT Clock
1
OSC
CLOCK
÷ 2
WDT Clock Symbol
WTX2
CKCON.6
59
4341D–MP3–04/05
ATMEL [ ATMEL ]
