TS68EN360
Figure 7-62. SPI Master (CP = 1)
167
160
166
SPICLK
CI=0
OUTPUT
161
160
163
SPICLK
CI=1
OUTPUT
166
161
162
LSB IN
SPIMISO
DATA
DATA
MSB
MSB IN
INPUT
165
164
SPIMOSI
OUTPUT
MSB OUT
167
LSB OUT
"1"
166
MSB
"1"
7.23 SPI Slave Electrical Specifications
Table 7-22. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-63 and Figure 7-64)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
Min
Max
Unit
tcyc
ns
170
171
172
173
174
175
176
177
178
179
180
181
182
Slave Cycle Time
2
15
15
1
–
2
15
15
1
–
Slave Enable Lead Time
Slave Enable Lag Time
ns
Slave Clock (SPICLK) High or Low Time
Slave Sequential Transfer Delay (Does Not Require Deselect)
Slave Data Setup Time (Inputs)
Slave Data Hold Time (Inputs)
Slave Access Time
–
–
tcyc
tcyc
ns
1
1
20
20
–
20
20
–
–
–
ns
50
50
50
–
50
50
50
–
ns
Slave SPIMISO Disable Time
Slave Data Valid (after SPICLK Edge)
Slave Data Hold Time (Outputs)
Rise Time: Input
ns
–
0
–
0
ns
ns
15
15
15
15
ns
Fall Time: Input
ns
69
2113B–HIREL–06/05
ATMEL [ ATMEL ]
