Figure 7-57. CAM Interface Receive Start Timing
RCLK1
RXD1
(INPUT)
1
1
0
Bit # 1
Bit # 2
START FRAME DELIMITER
135
136
RSTRT
(OUTPUT)
Note:
Valid for the ethernet protocol only.
Figure 7-58. CAM Interface Reject Timing
137
RRJCT
(INPUT)
Note:
Valid for the ethernet protocol only.
Figure 7-59. SDACK Timing Diagram
SDMA CYCLE
SE
S1
Sꢀ
S3
S4
S5
CLKO1
(OUTPUT)
AS
(OUTPUT)
138
139
SDACKx
(OUTPUT)
Note:
SDACKx is asserted when the SDMA writes the received Ethernet frame into memory.
66
TS68EN360
2113B–HIREL–06/05