TS68EN360
7.24 JTAG Electrical Specifications
Table 7-23. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-65 and Figure 7-68)
25.0 MHz
33.34 MHz
Number Characteristic
TCK Frequency of Operation
Min
Max
25
–
Min
Max
25
–
Unit
MHz
ns
0
40
18
0
0
40
18
0
1
2
TCK Cycle Time in Crystal Mode
TCK Clock Pulse Width Measured at 1.5V
TCK rise and Fall Times
–
–
ns
3
3
3
ns
6
Boundary Scan Input Data Setup Time
Boundary Scan Input Data Hold Time
TCK Low to Output Data Valid
TCK Low to Output High Impedance
TMS, TDI Data Setup Time
10
18
0
–
10
18
0
–
ns
7
–
–
ns
8
30
40
–
30
40
–
ns
9
0
0
ns
10
11
12
13
14
15
10
10
0
10
10
0
ns
TMS, TDI Data Hold Time
–
–
ns
TCK Low to TDO Data Valid
20
20
–
20
20
–
ns
TCK Low to TDO High Impedance
TRST Assert Time
0
0
ns
100
40
100
40
ns
TRST Setup Time to TCK Low
–
–
ns
Figure 7-65. Test Clock Input Timing Diagram
1
2
2
V
IH
TCK
(INPUT)
VM
VM
V
IL
3
3
Figure 7-66. TRST Timing Diagram
TCK
(INPUT)
15
TRST
(INPUT)
14
71
2113B–HIREL–06/05
ATMEL [ ATMEL ]
