7.22 SPI Master Electrical Specifications
Table 7-21. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-61 and Figure 7-62)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
1024
512
–
Min
Max
1024
512
–
Unit
tcyc
tcyc
ns
160
161
162
163
164
165
166
167
Master Cycle Time
4
2
4
2
Master Clock (SPICLK) High or Low Time
Master Data Setup Time (Inputs)
Master Data Hold Time (Inputs)
Master Data Valid (after SPICLK Edge)
Master Data Hold Time (Outputs)
Rise Time: Output
50
0
50
0
–
–
ns
–
20
–
–
20
–
ns
0
0
ns
15
15
15
15
ns
Fall Time: Output
ns
Figure 7-61. SPI Master (CP = 0)
167
166
SPICLK
CI=0
OUTPUT
167
161
160
SPICLK
CI=1
OUTPUT
166
161
162
163
SPIMISO
INPUT
LSB IN
MSB IN
MSB IN
DATA
165
164
SPIMOSI
OUTPUT
"1"
166
LSB OUT
DATA
MSB OUT
"1"
MSB OUT
167
68
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
