TS68EN360
8. Functional Description
8.1
CPU32+ Core
The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB and
apply the larger bus width. Although the original CPU32 core had a 32-bit internal data path and
32-bit arithmetic hardware, its interface to the IMB was 16 bits. The CPU32+ core can operate
on 32-bit external operands with one bus cycle. This allows the CPU32+ core to fetch a long-
word instruction in one bus cycle an to fetch two word-length instructions in one bus cycle, filling
the internal instruction queue more quickly. The CPU32+ core can also read and write 32-bit of
data in one bus cycle.
Although the CPU32+ instruction timings are improved, its instruction set is identical to that of
the CPU32. It will also execute the entire 68000 instruction set. It contains the same background
debug mode (BDM) features as the CPU32. No new compilers, assemblers or other software
support tools need be implemented for the CPU32+; standard CPU32 tools can be used.
The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted)
assumption that a 10-MHz 68000 delivers 1 VAX MIPS. If an application requires more perfor-
mance, the CPU32+ can be disabled, allowing the rest of the QUICC to operate as an intelligent
peripheral to a faster processor. The QUICC provides a special mode called TS68040 compan-
ion mode to allow it to conveniently interface to members of the TS68040 family. This two-chip
solution provides a 22-MIPS performance at 25 MHz.
The CPU32+ also offers automatic byte alignment features that are not offered on the CPU32.
These features allow 16- or 32-bit data to be read or written at an odd address. The CPU32+
automatically performs the number of bus cycles required.
8.2
System Integration Module (SIM60)
The SIM60 integrates general-purpose features that would be useful in almost any 32-bit pro-
cessor system. The term “SIM60” is derived from the QUICC part number, TS68EN360. The
SIM60 is an enhanced version of the SIM40 that exists on the TS68332 device.
First, new features, such as a DRAM controller and breakpoint logic, have been added. Second,
the SIM40 was modified to support a 32-bit IMB as well as a 32-bit external system bus. Third,
new configurations, such as slave mode and internal accesses by an external master, are
supported.
Although the QUICC is always a 32-bit device internally, it may be configured to operate with a
16-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is sup-
ported. Bus sizing allows 8-16-, and 32-bit peripherals and memory to exist in the 32-bit system
bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system bus mode.
8.3
Communications Processor Module (CPM)
The CPM contains features that allow the QUICC to excel in communications and control appli-
cations. These features may be divided into three sub-groups:
• Communications Processor (CP)
• Two IDMA Controllers
• Four General-purpose Timers
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2113B–HIREL–06/05
ATMEL [ ATMEL ]
