7.20 Ethernet Electrical Specifications
Table 7-19. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-54 to Figure 7-59)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
–
Min
Max
–
Unit
ns
120
121
CLSN Width High
40
–
40
–
RCLK1 Rise/Fall Time
15
15
ns
CLKO1 +
5 ns
CLKO1 +
5 ns
122
RCLK1 Width Low
–
–
123(1)
124
RCLK1 Width High
RXD1 Setup Time
RXD1 Hold Time
CLKO1
–
–
–
CLKO1
–
–
–
20
5
20
5
ns
ns
125
RENA Active Delay (from RCLK1 rising edge of the last
data bit)
126
10
–
10
–
ns
127
128
RENA Width Low
100
–
–
100
–
–
ns
ns
TCLK1 Rise/Fall Time
15
15
CLKO1 +
5 ns
CLKO1 +
5 ns
129
TCLK1 Width Low
–
–
130(1)
131
TCLK1 Width High
CLKO1
10
10
10
10
10
10
1
–
CLKO1
10
10
10
10
10
10
1
–
TXD1 Active Delay (from TCLK1 rising edge)
TXD1 Inactive Delay (from TCLK1 rising edge)
TENA Active Delay (from TCLK1 rising edge)
TENA Inactive Delay (from TCLK1 rising edge)
RSTRT Active Delay (from TCLK1 falling edge)
RSTRT Inactive Delay (from TCLK1 falling edge)
RRJCT Width Low
50
50
50
50
50
50
–
50
50
50
50
50
50
–
ns
ns
132
133
ns
134
ns
135
ns
136
ns
137
CLKO1
ns
138(2)
139(2)
CLKO1 Low to SDACK Asserted
–
20
20
–
20
20
CLKO1 Low to SDACK Negated
–
–
ns
Notes: 1. SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1
2. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Figure 7-54. Ethernet Collision Timing
CLSN (CTS1)
(INPUT)
120
64
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
