7.10 040 Bus Type Slave Mode Internal Read/Write/Lack Cycles AC Electrical Specifications
Table 7-9.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-26 to Figure 7-29)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
–
Min
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
251(1)
252
253
254
255
256
257
257
258(2)(3)
259
Address, Transfer Attributes Valid to Clock Low
15
7
5
0
0
0
4
4
4
–
–
–
–
–
–
–
–
–
11.25
TS Low to Clock High
–
6
3
0
0
0
4
4
4
–
–
–
–
–
–
–
–
–
–
Clock High to TS High
–
–
Clock high to Address, Transfer Attributes Invalid
Data-In, MBARE Valid to Clock High (040 Write)
Clock High to Data-In, MBARE Hold Time
Clock High to TA, TBI Low (External to External)
Clock High to TA, TBI Low (External to Internal)
Clock High to TA, TBI High
–
–
–
–
–
–
20
23
20
15
20
20
15
20
30
30
30
30
15
18
15
11.25
15
15
TA, TBI High to TA, TBI High Impedance
Clock Low to Data-Out Valid (040 Read)
Clock Low to Data-Out Invalid
260
262
263
Clock Low to Data-Out High Impedance
Clock High to AVECO Low
264
265
15
23
23
23
23
Clock Low to AVECO High Impedance
Clock Low to IACK Low
266
267
268
Clock High to IACK High
Clock Low to AVEC Low
Notes: 1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK.
2. When TS68040 is accessing the internal registers, specification 258 is from clock low not clock high.
3. The clock reference is EXTAL, not CLK01.TS68040 Internal Registers Read Cycles
40
TS68EN360
2113B–HIREL–06/05
ATMEL [ ATMEL ]
