TS68EN360
7.11 040 Bus Type SRAM/DRAM Cycles AC Electrical Specifications
Table 7-10. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary
(See Figure 7-30 to Figure 7-34)
25.0 MHz
33.34 MHz
Number Characteristic
Min
Max
20
–
Min
Max
15
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
280
280A
281
Address Valid to BADD2-3 Valid
–
15
0
–
10
0
BADD2-3 Valid to CAS Assertion
Address Invalid to BADD2-3 Invalid
Clock High to CSx/RASx Low (TSS40 = 0)
Clock High to CSx/RASx High (CSNT40 = 0)
Clock High to BRK Low
–
–
282
4
16
16
20
20
20
16
16
–
4
12
12
15
15
15
12
12
–
283
4
4
284
–
–
284A
285
Clock Low to BRK Low
–
–
Clock high to BRK High
–
–
286
Clock Low to CSx/RASx Low (TSS40 = 1)
Clock Low to CSx/RASx High (CSNT40 = 1)
Address Transfer Attributes Valid to Clock High (TSS40 = 0)
TA Low to Clock High (External Termination)
Clock High to TA High (External Termination)
Clock High to OE Low (Read Cycles)
Clock High to OE High (Read Cycles)
Clock High to WE Low (Write Cycles)
Clock High to WE High (Write Cycles)
Clock High to CASx Low
4
4
287
4
4
288(1)
289(2)
290(2)
291
10
11
–
10
9
–
–
20
20
20
20
20
13
13
13
16
16
20
–
–
15
15
15
15
15
10
10
10
12
12
15
–
–
–
292
–
–
293
–
–
294
–
–
295
4
4
295A
296(3)
297
Clock Low to CASx Low (040 Burst Read only)
Clock High to CASx High
4
4
4
4
Clock Low to AMUX Low
3
3
298
Clock High to AMUX High
3
3
299
Clock High to BADD2-3 Valid (040 Burst Cycles)
TEA Low to Clock High
4
4
300(2)
301(2)
302
11
2
Clock High to TEA High
20
–
2
6
5
–
15
–
Data, Parity Valid to Clock High (Data, Parity Setup)
Clock High to Data, Parity Invalid (Data, Parity Hold)
CLKO1 High (After TS Low) to Parity Valid
CLKO1 High (After TA Low) to Parity Hi-Z
7
303
7
–
–
305
–
20
20
15
15
306
4
Notes: 1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK.
2. TEA/TA should not be asserted on a DRAM burst access, or on the same clock or before RASx/CSx is asserted.
3. The clock reference is EXTAL, not CLK01.
43
2113B–HIREL–06/05
ATMEL [ ATMEL ]
