TS68EN360
Figure 7-22. DRAM: Refresh Cycle
S4
S5
S0
S1
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
106
CAS3-CAS0
(OUTPUT)
105A
12
12
9
RASx
(OUTPUT)
12A
RASx
(OUTPUT)
PAGE MODE
NOT IN PAGE MODE
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
Figure 7-23. DRAM: Page Mode – Page-Hit
S0
S1
S2
S3
S4
S5
S0
S1
S4
8
S5
S0
S1
CLKO1
(OUTPUT)
6A
6A
A31-A0
(OUTPUT)
108
11
INTERNAL MUX
INTERNAL MUX
107
107
AS
(OUTPUT)
9
100
101
RASx
(OUTPUT)
105
106
CAS3-CAS0
(OUTPUT)
105
121
111A
122
123
AMUX
(OUTPUT)
120
119
124
EXTERNAL MUX
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
37
2113B–HIREL–06/05