M67025E
Data-retention Mode
Atmel CMOS RAMs are designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The following rules ensure data
retention:
1. Chip select (CSL, CSR) must be held high during data retention; within VCC to
VCC - 0.2V.
2. CSL, CSR must be kept between VCC - 0.2V and 70% of VCC during the power
up and power down transitions.
3. The RAM can begin operation > tRC after VCC reaches the minimum operating
voltage (4.5 volts).
Timing
Parameter
Description
Minimum
Maximum
Unit
Data Retention
Voltage
VDR
2.0
–
V
Chip deselect to
data retention
time
TCDR
0
–
ns
Operation
recovery time
TR
TAVAV (1)
–
–
ns
Data retention
current
ICCDR1 (2)
400
µA
1.
2.
TAVAV = Read cycle time.
VIN (CSL/R) = Vcc
Vcc = 2V
V
V
IL = 0V
IH = Vcc
12
4146J–AERO–06/03
ATMEL [ ATMEL ]
