The write pulse to the SLAVE must be inhibited by the MASTER’s maximum arbitration
time. If a conflict then occurs, the write to the SLAVE will be inhibited because of the
MASTER’s BUSY signal.
Semaphore Logic
The M67025E is an extremely fast dual-port 4 Kb × 16 CMOS static RAM with an additional
locations dedicated to binary semaphore flags. These flags allow either of the processors on the
left or right side of the dual-port RAM to claim priority over the other for functions defined by the
system software. For example, the semaphore flag can be used by one processor to inhibit the
other from accessing a portion of the dual-port RAM or any other shared resource.
The dual-port RAM has a fast access time, and the two ports are completely indepen-
dent of each another. This means that the activity on the left port cannot slow the access
time of the right port. The ports are identical in function to standard CMOS static RAMs
and can be read from, or written to, at the same time with the only possible conflict aris-
ing from simultaneous writing to, or a simultaneous READ/WRITE operation on, a non-
semaphore location. Semaphores are protected against such ambiguous situations and
may be used by the system program to prevent conflicts in the non-semaphore segment
of the dual-port RAM. The devices have an automatic power-down feature controlled by
CS, the dual-port RAM select and SEM, the semaphore enable. The CS and SEM pins control
on-chip-power-down circuitry that permits the port concerned to go into stand-by mode when
not selected. This conditions is shown in Table 1 where CS and SEM are both high.
Systems best able to exploit the M67025E are based around multiple processors or con-
trollers and are typically very high-speed, software controlled or software-intensive
systems. These systems can benefit from the performance enhancement offered by the
M67025 hardware semaphores, which provide a lock-out mechanism without the need
for complex programming.
Software handshaking between processors offers the maximum level of system flexibil-
ity by permitting shared resources to be allocated in varying configurations. The
M67025E does not use its semaphore flags to control any resources through hardware,
thus allowing the system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more usual methods of hardware
arbitration is that neither processor ever incurs wait states. This can prove to be a con-
siderable advantage in very high speed systems.
How The Semaphore
Flags Work
The semaphore logic is a set of eight latches independent of the dual-port RAM. These
latches can be used to pass a flag or token, from one port to the other to indicate that a
shared resource is in use. The semaphore provides the hardware context for the “Token
Passing Allocation’ method of use assignment. This method uses the state of a sema-
phore latch as a token indicating that a shared resource is in use. If the left processor
needs to use a resource, it requests the token by setting the latch. The processor then
verifies that the latch has been set by reading it. If the latch has been set the processor
assumes control over the shared resource. If the latch has not been set, the left proces-
sor has established that the right processor had set the latch first, has the token and is
using the shared resource. The left processor may then either repeatedly query the sta-
tus of the semaphore, or abandon its request for the token and perform another
operation whilst occasionally attempting to gain control of the token through a set and
test operation. Once the right side has relinquished the token the left side will be able to
take control of the shared resource.
The semaphore flags are active low. A token is requested by writing a zero to a sema-
phore latch, and is relinquished again when the same side writes a one to the latch.
5
M67025E
4146J–AERO–06/03
ATMEL [ ATMEL ]
