5962-0520802QYC 参数 Datasheet PDF下载

Figure 5.

Write Cycle 3. CS Controlled

(1)

E

Note:

The internal write time of the memory is defined by the overlap of CS Low and W LOW. Both signals must be activated to initiate

a write and either signal can terminate a write by going in active mode. The data input setup and hold timing should be refer-

enced to the active edge of the signal that terminates the write.

Data out is high impedance if OE= V

IH

.

9

AT60142F

4408G–AERO–04/09