AT60142F
Data Retention Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The following rules insure data
retention:
1. During data retention chip select CS must be held high within
V
CC
to
V
CC
-0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high imped-
ance, minimizing power dissipation.
3. During power-up and power-down transitions CS and OE must be kept between
V
CC
+ 0.3V and 70% of
V
CC
.
4. The RAM can begin operation > t
R
ns after
V
CC
reaches the minimum operation
voltages (3V).
Figure 1.
Data Retention Timing
Data Retention Characteristics
Parameter
V
CCDR
Description
V
CC
for data
retention
Chip deselect
to data
retention time
Operation
recovery time
Data retention
current
T
AVAV
= Read cycle time.
CS = V
CC
, V
IN
= GND/V
CC
.
Min
2.0
Typ T
A
= 25°C
–
Max
–
Unit
V
t
CDR
0.0
–
–
ns
t
R
I
CCDR (2)
1.
2.
t
AVAV
–
(1)
–
0.700
–
1.3
ns
mA
6
4408G–AERO–04/09
ATMEL [ ATMEL CORPORATION ]
