Port Width / Address
(hex)
32
18
19
1A
1B
1C
1D
1E
1F
20
16
18
19
1A
1B
1C
1D
1E
1F
20
8
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
CH1_COMICFG
CH1_TX_SAR
Register
CH1_CNTRL1
CH1_CNTRL2
CH1_HTID
CH1_HCNTRL
CH1_ESR1
CH1_ESR2
Function
channel 1 control Register 1
channel 1 control Register 2
channel 1 Header Transaction ID byte
channel 1 Header control byte
channel 1 detailed error source register 1
channel 1 detailed error source register 2
reserved
channel 1 COMI configuration register
channel 1 transmit Start Address Register
Reset Value
(hex)
00
00
00
00
00
00
00
00
0000
Access
r/w
r/w
ro
ro
r/w
r/w
---
r/w
r/w
22
22
CH1_TX_EAR
channel 1 transmit End Address Register
0000
r/w
24
26
27
28
24
26
27
28
CH1_TX_CAR
CH1_TX_FIFO
CH1_TX_EOPB
CH1_RX_SAR
channel 1 transmit Current Address Register
channel 1 transmit FIFO
channel 1 transmit EOP Bit Register
channel 1 receive Start Address Register
0000
--
--
0000
ro
wo
wo
r/w
2A
2A
CH1_RX_EAR
channel 1 receive End Address Register
0000
r/w
2C
2E
2F
2C
2E
2F
CH1_RX_CAR
CH1_RX_FIFO
CH1_STAR
channel 1 receive Current Address Register
channel 1 receive FIFO
channel 1 Status Register
0000
xxxxxxxx
01
ro
ro
ro
TSS901E channel 2 status and control registers
Port Width / Address
(hex)
32
30
31
32
33
34
35
16
30
31
32
33
34
35
8
30
31
32
33
34
35
Register
CH2_DSM_MODR
CH2_DSM_CMDR
CH2_DSM_STAR
CH2_DSM_TSTR
CH2_ADDR
CH2_RT_ADDR
Function
channel 2 DSM mode Register
channel 2 DSM command Register
channel 2 DSM status Register
channel 2 DSM test Register
channel 2 address Register
channel 2 Route Address Register
Reset Value
(hex)
03
00
00
00
00
00
Access
r/w
r/w
r/w
r/w
r/w
r/w
9
TSS901E
Rev. C – 24-Aug-01
ATMEL [ ATMEL CORPORATION ]
