Port Width / Address
(hex)
Reset Value
(hex)
32
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
16
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
8
Register
Function
Access
r / w
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
CH3_DSM_TSTR
CH3_ADDR
channel 3 DSM test Register
channel 3 address Register
channel 3 Route address Register
channel 3 Protocol Status Register
reserved
00
00
00
04
00
00
00
00
00
00
00
00
00
r / w
CH3_RT_ADDR
CH3__PR_STAR
r / w
r / w
CH3_CNTRL1
CH3_CNTRL2
CH3_HTID
channel 3 control Register 1
channel 3 control Register 2
channel 3 Header Transaction ID byte
channel 3 Header control byte
channel 3 detailed error source register 1
channel 3 detailed error source register 2
reserved
r / w
r / w
ro
CH3_HCNTRL
CH3_ESR1
ro
r / w
r / w
CH3_ESR2
CH3_COMICFG
CH3_TX_SAR
channel 3 COMI configuration register
r / w
r / w
60
61
60
62
64
60
62
64
channel 3 transmit Start Address Register
channel 3 transmit End Address Register
channel 3 transmit Current Address Register
00
00
00
62
63
CH3_TX_EAR
CH3_TX_CAR
r / w
ro
64
65
66
67
66
67
66
67
CH3_TX_FIFO
CH3_TX_EOPB
channel 3 transmit FIFO
00
00
wo
wo
channel 3 transmit EOP Bit Register
68
69
68
6A
6C
68
6A
6C
CH3_RX_SAR
CH3_RX_EAR
CH3_RX_CAR
channel 3 receive Start Address Register
channel 3 receive End Address Register
channel 3 receive Current Address Register
00
00
00
r / w
r / w
ro
6A
6B
6C
6D
6E
6F
6E
6F
6E
6F
CH3_RX_FIFO
CH3_STAR
channel 3 receive FIFO
xxxxxxxx
01
ro
ro
channel 3 Status Register
11
TSS901E
Rev. C – 24-Aug-01
ATMEL [ ATMEL ]
