TSS901E
Port Width / Address
(hex)
Reset Value
32
36
37
38
39
3A
3B
3C
3D
3E
3F
16
36
37
38
39
3A
3B
3C
3D
3E
3F
8
Register
Function
(hex)
Access
36
37
38
39
3A
3B
3C
3D
3E
3F
CH2_PR_STAR
channel 2 Protocol Status Register
reserved
04
r / w
00
CH2_CNTRL1
CH2_CNTRL2
CH2_HTID
channel 2 control Register 1
channel 2 control Register 2
channel 2 Header Transaction ID byte
channel 2 Header control byte
channel 2 detailed error source register 1
channel 2 detailed error source register 2
reserved
00
r / w
r / w
ro
00
00
CH2_HCNTRL
CH2_ESR1
00
ro
00
r / w
r / w
CH2_ESR2
00
00
CH2_COMICFG
CH2_TX_SAR
channel 2 COMI configuration register
00
r / w
r / w
40
41
40
42
44
40
42
44
channel 2 transmit Start Address Register
channel 2 transmit End Address Register
channel 2 transmit Current Address Register
00
00
00
42
43
CH2_TX_EAR
CH2_TX_CAR
r / w
ro
44
45
46
47
46
47
46
47
CH2_TX_FIFO
CH2_TX_EOPB
channel 2 transmit FIFO
00
00
wo
wo
channel 2 transmit EOP Bit Register
48
49
48
4A
4C
48
4A
4C
CH2_RX_SAR
CH2_RX_EAR
CH2_RX_CAR
channel 2 receive Start Address Register
channel 2 receive End Address Register
channel 2 receive Current Address Register
00
00
00
r / w
r / w
ro
4A
4B
4C
4D
4E
4F
4E
4F
4E
4F
CH2_RX_FIFO
CH2_STAR
channel 2 receive FIFO
xxxxxxxx
01
ro
ro
channel 2 Status Register
TSS901E channel 3 status and control registers
Port Width / Address
(hex)
Reset Value
(hex)
32
50
51
52
16
50
51
52
8
Register
Function
Access
r / w
50
51
52
CH3_DSM_MODR
CH3_DSM_CMDR
CH3_DSM_STAR
channel 3 DSM mode Register
channel 3 DSM command Register
channel 3 DSM status Register
03
00
00
r / w
r / w
10
Rev. C – 24-Aug-01
ATMEL [ ATMEL ]
