TSC695F
Table 1. Pin Descriptions (Continued)
Signal
Type
Active
Description
OE
O
O
O
O
O
O
O
I
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
Low
High
Low
High
High
High
High
High
Memory output enable
Data buffer enable
Output buffer: 400 pF
BUFFEN
DDIR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Data buffer direction
Data buffer direction
I/O chip select
DDIR
IOSEL[3:0]
IOWR
I/O and exchange memory write strobe
Exchange memory chip select
Bus ready
EXMCS
BUSRDY
BUSERR
DMAREQ
DMAGNT
DMAAS
DRDY
I
Bus error
I
DMA request
O
I
DMA grant
DMA address strobe
Data ready during DMA access
IU error
O
O
O
O
I
IUERR
CPUHALT
SYSERR
SYSHALT
SYSAV
NOPAR
INULL
Processor (IU & FPU) halt and freeze
System error
System halt
O
I
System availability
No parity
O
O
O
O
O
I
Integer unit nullify cycle
Instruction fetch
INST
Used to check the execute
stage of IU
FLUSH
DIA
FPU instruction flush
Delay instruction annulled
Real Time Clock Counter output
Receive data UART ’A’ and ’B’
Transmit data UART ’A’ and ’B’
GPI input/output
instruction pipeline
RTC
-
RxA/RxB
TxA/TxB
GPI[7:0]
GPIINT
EXTINT[4:0]
EXTINTACK
IWDE
Input trigger
O
I/O
O
I
-
Input trigger
High
GPI interrupt
-
External interrupt
Input trigger
O
I
High
High
High
External interrupt acknowledge
Internal watch dog enable
External watch dog input interrupt
Watch dog clock
-
-
EWDINT
WDCLK
CLK2
I
Input trigger
I
-
I
Double frequency clock
System clock
-
SYSCLK
RESET
SYSRESET
TMODE[1:0]
DEBUG
TCK
O
O
I
-
Low
Low
Output reset
-
System input reset
Factory test mode
Input trigger
I
Functional mode=00
I
High
Low
Software debug mode
Test (JTAG) clock
-
I
-
TRST
I
Test (JTAG) reset
pull-up ≈ 37 kΩ
TMS
I
Test (JTAG) mode select
Test (JTAG) data input
Test (JTAG) data output
Main internal power
Output driver power
pull-up ≈ 37 kΩ
TDI
I
pull-up ≈ 37 kΩ
TDO
O
-
-
-
VCCI/VSSI
VCCO/VSSO
Note:
If not specified, the output buffer type is 150 pF, the input buffer type is TTL.
3
4118H–AERO–06/03
ATMEL [ ATMEL ]
