Table 4. Synchronous Traps (Continued)
Trap
Priority
Trap Type (tt) Comments
Idem “instruction access”
Data access exception
(Error on data load)
10
11
12
09h
System register access violation
Tag overflow
0Ah
TADDccTV and TSUBccTV instructions
Trap on integer condition codes (Ticc)
Trap instructions
80h to FFh
Table 5. Interrupts or Asynchronous Traps
Trap
Priority
Comments
Trap Type (tt)
1Fh
Watchdog time-out
External INT 4
13
Internal or external (EWDINT pin)
14
1Eh
EXTINTAK on only one of EXTINT[4:0]
Real time clock timer
General purpose timer
External INT 3
15
1Dh
–
16
1Ch
–
17
1Bh
EXTINTAK on only one of EXTINT[4:0]
External INT 2
18
1Ah
EXTINTAK on only one of EXTINT[4:0]
DMA time-out
19
19h
–
DMA access error
UART Error
20
18h
–
21
17h
–
Correctable error in memory
Data ready
22
16h
Data read OK but source not updated
–
UART B
Transmitter ready
23
15h
Data ready
Transmitter ready
–
UART A
24
25
26
14h
13h
12h
External INT 1
External INT 0
EXTINTAK on only one of EXTINT[4:0]
EXTINTAK on only one of EXTINT[4:0]
Logical OR of:
IU hardware error masked
IU error mode masked
System hardware error masked
Masked hardware errors
27
11h
It is possible to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register
are cleared automatically when the interrupt is acknowledged.
By programming the Interrupt Shape Register, it is possible to define the external interrupts to either be active low or active
high and to define the external interrupts to either be edge or level sensitive.
10
TSC695F
4118H–AERO–06/03
ATMEL [ ATMEL ]
