ware layout, increases system reliability, minimizes switch-
ing noise, and reduces package size and active pin count.
The device is optimized for use in many commercial and
industrial applications where high density, low pin count,
low voltage, and low power are essential. Typical applica-
tions for the DataFlash are digital voice storage, image
storage, and data storage. The device operates at clock
frequencies up to 13 MHz with a typical active read current
consumption of 4 mA.
To allow for simple in-system reprogrammability, the
AT45DB011 does not require high input voltages for pro-
gramming. The device operates from a single power sup-
p ly , 2. 7V to 3. 6V , f o r b o th t he pr o g r am an d r e a d
operations. The AT45DB011 is enabled through the chip
select pin (CS) and accessed via a three-wire interface
consisting of the Serial Input (SI), Serial Output (SO), and
the Serial Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER (264 BYTES)
SCK
CS
RESET
V
CC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
Memory Array
To provide optimal flexibility, the memory array of the
AT45DB011 is divided into three levels of granularity com-
prising of sectors, blocks, and pages. The Memory Archi-
tecture Diagram illustrates the breakdown of each level and
details the number of pages per sector and block. All pro-
gram operations to the DataFlash occur on a page by page
basis; however, the optional erase operations can be per-
formed at the block or page level.
2
AT45DB011
ATMEL [ ATMEL CORPORATION ]
