45DB011B 参数 Datasheet PDF下载

AT45DB011

Reset Timing (Inactive Clock Polarity Low Shown)

CS

tREC

tCSS

SCK

tRST

RESET

HIGH IMPEDANCE

HIGH IMPEDANCE

SO

SI

Command Sequence for Read/Write Operations (Except Status Register Read)

SI

CMD

8 bits

8 bits

8 bits

MSB

r r r r

r r XX

XXXX XXXX

Page Address

(PA8-PA0)

XXXX XXXX

LSB

Reserved for

larger densities

Byte/Buffer Address

(BA8-BA0/BFA8-BFA0)

Notes:

1.

2.

3.

“r” designates bits reserved for larger densities.

It is recommended that “r” be a logical “0”.

For densities larger than 1M bit, the “r” bits become the most significant Page Address bit for the appropriate density.

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