AC Waveforms
Two different timing diagrams are shown below. Waveform
1 shows the SCK signal being low when CS makes a high-
to-low transition, and Waveform 2 shows the SCK signal
being high when CS makes a high-to-low transition. Both
waveforms show valid timing diagrams. The setup and hold
times for the SI signal are referenced to the low-to-high
transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI
Mode 0, and Waveform 2 shows timing that is compatible
with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low
tCS
CS
tCSS
SCK
tV
SO
HIGH IMPEDANCE
tSU
SI
VALID IN
tH
tHO
VALID OUT
tDIS
HIGH IMPEDANCE
tWH
tWL
tCSH
Waveform 2 – Inactive Clock Polarity High
tCS
CS
tCSS
SCK
tV
SO
HIGH Z
tSU
SI
VALID IN
tHO
VALID OUT
tH
tDIS
HIGH IMPEDANCE
tWL
tWH
tCSH
8
AT45DB011
ATMEL [ ATMEL CORPORATION ]
