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APW7120KE-TRL 参数 Datasheet PDF下载

APW7120KE-TRL图片预览
型号: APW7120KE-TRL
PDF下载: 下载PDF文件 查看货源
内容描述: 5V至12V电源电压, 8引脚,同步降压PWM控制器 [5V to 12V Supply Voltage, 8-PIN, Synchronous Buck PWM Controller]
分类和应用: 控制器
文件页数/大小: 20 页 / 805 K
品牌: ANPEC [ ANPEC ELECTRONICS COROPRATION ]
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APW7120  
Application Information (Cont.)  
Layout Considerations (Cont.)  
5. Use an dedicated trace to connect the ROCSET  
and the Drain padof the low-side MOSFET, Kevin  
connection , for accurate current sensing.  
finally combined using ground plane construction or  
single point grounding. Figure 2 illustrates the layout,  
with bold lines indicating high current paths.  
Components along the bold lines should be placed  
close together. Below is a checklist for your layout:  
6. Keep the switching nodes (UGATE, LGATE and  
PHASE) away from sensitive small signal nodes  
since these nodesare fast moving signals. Therefore  
keep traces to these nodes as short as possible.  
1. Begin the layout by placing thepower components  
first. Orient the power circuitry to chieve a clean  
power flowpath. If possible make all the connections  
on one side of the PCB with wide, copper filled  
areas.  
7. Place thedecoupling ceramic capacitor CHF near  
the Drain of the high-side MOSFET as close as  
possible. The bulk capacitors CIN are also placed  
near the Drain.  
2. Connect the ground of feedback divider directly  
to the GND pin of the IC using a dedicated ground  
trace.  
8. Place the Source of the high-side MOSFET and  
theDrainof thelow-sideMOSFETasclosepossible.  
Minimizing the impedance with wide layout plane  
between the two padsreduces the voltage bounce  
of the node.  
3. The VCC decoupling capacitor should be right  
next to the VCC and GND pins. Capacitor CBOOT  
should be connected as close to the BOOT and  
PHASE pins as possible.  
9. Use a wide power ground plane, with low  
impedance, to connects the CHF, CIN, COUT  
,
Schottky diode and the Source of the low-side  
MOSFETtoprovidealowimpedancepathbetween  
the components for large and high frequency  
switching currents.  
4. Minimize the length and increase the width of  
the trace between UGATE/LGATE and the gates  
of the MOSFETs to reduce the impedance driving  
the MOSFETs.  
V
IN  
CHF  
C
IN  
5
VCC  
+
1
BOOT  
4
LGATE  
APW7120  
2
8
COUT  
Q1  
UGATE  
Q2  
+
PHASE  
L1  
VOUT  
Figure 2 Recommended Layout Diagram  
Copyright ã ANPEC Electronics Corp.  
Rev. A.4 - Jan., 2006  
16  
www.anpec.com.tw  
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